![]() Tomasevic, M., Milutinovic, V.: Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors. IEEE Computer Society Press, Los Alamitos (1993) Tomasevic, M., Milutinovic, V.: The Cache Coherence Problem in Shared-Memory Multiprocessors –Hardware Solutions. Sweazey, P., Smith, A.J.: A Class of Compatible Cache Consistency Protocols and Their Support by the IEEE Futurebus. Stunkel, C.B., Janssens, B., Fuchs, W.K.: Address Tracing for Parallel Machines. on Computer Architecture, San Diego, CA (May 1993) Stenstrom, P., Brorsson, M., Sandberg, L.: An Adaptive Cache Coherence Protocol Optimezed for Migratory Sharing. IEEE Transactions on Parallel and Distributed Systems 4(2), 131–143 (1993) Squillante, M.S., Lazowska, D.E.: Using Processor-Cache Affinity Information in Shared-Memory Multiprocessor Scheduling. APACHE – An HTTP Server, Reference Manual (1995) ![]() Prete, C.A., Prina, G., Giorgi, R., Ricciardi, L.: Some Considerations About Passive Sharing in Shared-Memory Multiprocessors. IEEE Transactions on Parallel and Distributed Systems 6(9), 915–929 (1995) Prete, C.A., Prina, G., Ricciardi, L.: A Trace Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor System. Prete, C.A.: RST Cache Memory Design for a Tightly Coupled Multiprocessor System. Prete, C.A.: A new solution of coherence protocol for tightly coupled multiprocessor systems. Jeremiassen, T.E., Eggers, S.J.: Reducing False Sharing on Shared Memory Multiprocessors through Compile Time Data Transformations. Journal of Parallel and Distributed Computing 34(2), 183–195 (1996) Hyde, R.L., Fleisch, B.D.: An Analysis of Degenerate Sharing and False Coherence. Morgan Kaufmann Publishers, San Francisco (1996) Hennessy, J., Petterson, D.A.: Computer Architecture: a Quantitative Approach, 2nd edn. IEEE Transactions on Parallel and Distributed Systems 10(7), 742–763 (1999) Giorgi, R., Prete, C.A.: PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. Giorgi, R., Prete, C.A., Prina, G., Ricciardi, L.: Trace Factory: a Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessor. Giorgi, R., Prete, C., Prina, G., Ricciardi, L.: A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. ![]() on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, pp. Gharachorloo, K., Gupta, A., Hennessy, J.: Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors. 98–108 (May 1993)Įdwards, J.: The changing Face of Freeware. on Computer Architecture, San Diego, California, pp. 3–14 (June 1998)Ĭox, A.L., Fowler, R.J.: Adaptive Cache Coherency for Detecting Migratory Shared Data. Internet Computing 1(2), 18–27 (1997)īarroso, L.A., Gharachorloo, K., Bugnion, E.: Memory System Characterization of Commercial Workloads. 215–225 (May 1998)īaentsch, M., Baum, L., Molter, G.: Enhancing the Web’s Infrastructure: From Caching to Replication. This process is experimental and the keywords may be updated as the learning algorithm improves.Īgarwal, A., Gupta, A.: Memory Reference Characteristics of Multiprocessor Applications under Mach. These keywords were added by machine and not by the authors. The evaluation of two of such protocols (AMSD and PSCR) shows that we can achieve better processor utilization compared to the MESI case. Passive sharing can be reduced, or even eliminated, by using appropriate coherence protocols. In order to limit false sharing overhead, we can adopt an accurate design of kernel data structures. The results show that even though the performance may take advantage of larger caches or from cache affinity scheduling, there is still a great amount of passive sharing, besides false sharing and active sharing. ![]() Then, we consider the sixteen-processor case, where the effects on performance are more massive. We show that, even in the four-processor case, the overhead induced by the sharing of private data as a consequence of process migration, namely passive sharing, cannot be neglected. We analyze a basic four-processor and a high-performance sixteen-processor machine. Nevertheless, many factors that influence bus utilization, when process migration is permitted, have not been thoroughly investigated yet. It is well known that, in this kind of system, the bus is the critical element that may limit the scalability of the machine. We considered a shared-bus shared-memory multiprocessor as the simplest multiprocessor architecture to be used for accelerating Web-based and commercial applications. In this work we put into evidence how the memory performance of a Web-Server machine may depend on the sharing induced by process migration.
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